//
//	PRU.abl	MC68HC16 RPU(Port Replacement Unit)
//		for Xilinx XC9572
//		Copyright(C)2002 By H.Kashima
//
MODULE PRU
Declarations
	D0..D7		pin 1,2,3,4,5,6,7,8;
	D8..D14		pin 18,19,20,22,24,25,26;
	PH0..PH7	pin 28,29,33,34,35,36,37,38 istype 'reg_d';
	PE4..PE7	pin 43,44,9,27 istype 'reg_d';
	A0..A3		pin 11,12,13,14;
	CSE,RW,RESET	pin 42,40,39;

	ddrh7..ddrh0	node istype 'reg_d';

	dbh = [D14..D8];
	dbl = [D7..D0];
	porth = [PH7..PH0];
	porte = [PE7..PE4];
	ab = [A3..A0];
	ddrh = [ddrh7..ddrh0];

	ioporta = ( ab == ^h00a );
	ioportb = ( ab == ^h00b );
	ioportg = ( ab == ^h00c );
	ioporth = ( ab == ^h00d );
	ioddrg  = ( ab == ^h00e );
	ioddrh  = ( ab == ^h00f );
	ioporte0 = ( ab == ^h001 );
	ioporte1 = ( ab == ^h003 );
	ioddrab = ( ab == ^h004 );
	ioddre  = ( ab == ^h005 );
	iopepar = ( ab == ^h007 );

EQUATIONS
// CPU configuration data
when( !RESET * RW ) then {
	dbh =  ^b0111001;
	dbl = ^b11111101;
	dbh.oe =  ^b1111111;
	dbl.oe = ^b11111111;
}

dbh.oe =  ^b0000000;
dbl.oe = ^b00000000;

//PORT.E
when((ioporte0 + ioporte1) * RW * !CSE ) then {
	[D7..D4] = porte.pin;
	[D3..D0] = ^b1111;
	dbl.oe = ^b11111111;
}
when( ioddre * RW * !CSE ) then {
	[D7..D4] = ^b1111;
	[D3..D0] = ^b0000;
	dbl.oe = ^b11111111;
}
porte := [D7..D4];
porte.oe = ^b1111;
!porte.clk = !RW * (ioporte0 + ioporte1) * !CSE;
porte.ar = !RESET;

//
//PORT.H
when( ioporth * RW * !CSE ) then {
	dbl = porth.pin;
	dbl.oe = ^b11111111;
}
when( ioddrh * RW * !CSE ) then {
	dbl = ddrh.fb;
	dbl.oe = ^b11111111;
}
ddrh := dbl;
!ddrh.clk = !RW * ioddrh * !CSE;
ddrh.ar = !RESET;
porth := dbl;
porth.oe = ddrh.fb;
!porth.clk = !RW * ioporth * !CSE;
porth.ar = !RESET;

END